library verilog;
use verilog.vl_types.all;
entity mem_U0 is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        adr             : in     vl_logic_vector(13 downto 0);
        dat_i           : in     vl_logic_vector(7 downto 0);
        dat_o           : out    vl_logic_vector(7 downto 0);
        we              : in     vl_logic;
        en              : in     vl_logic
    );
end mem_U0;
